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this is information on a product in full production. june 2014 docid023924 rev 4 1/38 m24c08-w m24c08-r m24c08-f 8-kbit serial i2c bus eeprom datasheet - production data 1. not recommended for new designs features ? compatible with all i 2 c bus modes: ? 400 khz ? 100 khz ? memory array: ? 8 kbit (1 kbyte) of eeprom ? page size: 16 bytes ? single supply voltage: ? m24c08-w: 2.5 v to 5.5 v ? m24c08-r: 1.8 v to 5.5 v ? m24c08-f: 1.7 v to 5.5 v (full temperature range) and 1.6 v to1.7 v (limited temperature range) ? write: ? byte write within 5 ms ? page write within 5 ms ? operating temperature range: from -40 c up to +85 c ? random and sequential read modes ? write protect of the whole memory array ? enhanced esd/latch-up protection ? more than 4 million write cycles ? more than 200-year data retention packages ? pdip8 ecopack1 ? ? so8 ecopack2 ? ? tssop8 ecopack2 ? ? ufdfpn8 ecopack2 ? ? wlcsp ecopack2 ? pdip8 (bn) (1) tssop8 (dw) 169 mil width ufdfpn8 (mc) so8 (mn) 150 mil width wlcsp (ct) www.st.com
contents m24c08-w m24c08-r m24c08-f 2/38 docid023924 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 17 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 docid023924 rev 4 3/38 m24c08-w m24c08-r m24c08-f contents 3 6 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 list of tables m24c08-w m24c08-r m24c08-f 4/38 docid023924 rev 4 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. operating conditions (voltage range w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. operating conditions (voltage range r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. operating conditions (voltage range f, for devices identified by process letter t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. operating conditions (voltage ra nge f, for all other devices) . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. dc characteristics (m24c08-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. dc characteristics (m24c08-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. dc characteristics (m24c08-f device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. 100 khz ac characteristics (i 2 c standard mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 30 table 19. so8n ? 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 31 table 20. pdip8 ? 8-pin plastic dip, 0.25 mm lead fram e, package mechanical data. . . . . . . . . . . . 32 table 21. ufdfpn8 (mlp8) ? package dime nsions (ufdfpn: ult ra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22. m24c08-fct6tp/t package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 23. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 docid023924 rev 4 5/38 m24c08-w m24c08-r m24c08-f list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. wlcsp connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7 figure 4. chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 10. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31 figure 16. pdip8 ? 8-pin plastic dip, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 32 figure 17. ufdfpn8 (mlp8) ? package outline (ufdfpn: ultra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18. m24c08-fct6tp/t package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19. wlcsp 4-bump wafer-level chip-scale package recommended land pattern . . . . . . . . . . 35 description m24c08-w m24c08-r m24c08-f 6/38 docid023924 rev 4 1 description the m24c08 is an 8-kbit i 2 c-compatible eeprom (electri cally erasable programmable memory) organized as 1 k 8 bits. the m24c08-w can be accessed with a supply voltage from 2.5 v to 5.5 v, the m24c08-r can be accessed with a supply voltage from 1.8 v to 5.5 v, and the m24c08-f can be accessed either with a supply voltage from 1.7 v to 5.5 v (over the full temperature range) or with an extended supply voltage from 1.6 v to 1.7 v. all these devices operate with a clock frequency of 400 khz. figure 1. logic diagram table 1. signal names signal name function direction e2 (1) 1. signal not connected in the wlcsp package. chip enable input sda serial data i/o scl serial clock input wc (1) write control input v cc supply voltage - v ss ground - - 3 6 3 $ ! 6 # # - x x x 7 # 3 # , 6 3 3 % docid023924 rev 4 7/38 m24c08-w m24c08-r m24c08-f description 37 figure 2. 8-pin package connections, top view 1. nc: not connected. 2. see section 9: package mechanical data for package dimensions, and how to identify pin 1 figure 3. wlcsp connections (top view, ma rking side, with balls on the underside) 1. the e2 and wc inputs are not connected to a ball, ther efore e2 input is decoded as ?0? (see also section 2.3: chip enable (e2) ) and the device remains always ac cessible in write mode (see also section 2.4: write control (wc) ). 0 6 9 ^ s ^ ^ ^ > t e e s ? ? ? e ? ? 0 6 9 ^ > { ^ s s ^ ^ ? 3 , 1 $ 0 d u n l q j v l g h w r s y l h z % x p s v l g h e r w w r p y l h z ^ > ^ s s ^ ^ ? signal description m24c08-w m24c08-r m24c08-f 8/38 docid023924 rev 4 2 signal description 2.1 serial clock (scl) the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be co nnected from serial data (sda) to v cc ( figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 chip enable (e2) this input signal is used to set the value that is to be looked for on the bit b3 of the device select code. this input must be tied to v cc or v ss , to establish the device select code as shown in figure 4 . when not connected (left floating), this input is read as low (0). figure 4. chip enab le inputs connection 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disa bled to the entire memory array when write control ( wc ) is driven high. write operations are enabled when write control ( wc ) is either driven low or left floating. when write control ( wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i docid023924 rev 4 9/38 m24c08-w m24c08-r m24c08-f signal description 37 2.5 v ss (ground) v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 8: dc and ac parameters ) . in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ) and the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 8: dc and ac parameters ). in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). memory organization m24c08-w m24c08-r m24c08-f 10/38 docid023924 rev 4 3 memory organization the memory is organized as shown below. figure 5. block diagram - 3 6 7 # # o n t r o l l o g i c ( i g h v o l t a g e g e n e r a t o r ) / s h i f t r e g i s t e r ! d d r e s s r e g i s t e r a n d c o u n t e r $ a t a r e g i s t e r p a g e 8 d e c o d e r 9 d e c o d e r % 3 # , 3 $ ! docid023924 rev 4 11/38 m24c08-w m24c08-r m24c08-f device operation 37 4 device operation the device supports the i 2 c protocol. this is summarized in figure 6 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a dat a transfer can only be initia ted by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 6. i 2 c bus protocol 3 # , 3 $ ! 3 # , 3 $ ! 3 $ ! 3 4 ! 2 4 # o n d i t i o n 3 $ ! ) n p u t 3 $ ! # h a n g e ! ) " 3 4 / 0 # o n d i t i o n - 3 " ! # + 3 4 ! 2 4 # o n d i t i o n 3 # , - 3 " ! # + 3 4 / 0 # o n d i t i o n device operation m24c08-w m24c08-r m24c08-f 12/38 docid023924 rev 4 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is followed by noack can be fo llowed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. docid023924 rev 4 13/38 m24c08-w m24c08-r m24c08-f device operation 37 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start conditio n. following this, the bus master s ends the device select code, shown in table 2 (on serial data (sda), most significant bit first). the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the de vice does not match the device select code, it de selects itself from the bus, and goes into standby mode. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address rw b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 e2 a9 a8 rw instructions m24c08-w m24c08-r m24c08-f 14/38 docid023924 rev 4 5 instructions 5.1 write operations following a start condition the bus master sends a device select code with the r/ w bit (r w ) reset to 0. the device acknowledges this, as shown in figure 7 , and waits for the address byte. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is triggered. a stop condition at any othe r time slot does not trigger the internal write cycle. after the stop condition and the successful completion of an internal write cycle (t w ), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 8 . table 3. address byte a7 a6 a5 a4 a3 a2 a1 a0 docid023924 rev 4 15/38 m24c08-w m24c08-r m24c08-f instructions 37 5.1.1 byte write after the device select code and the address by te, the bus master sends one data byte. if the addressed location is write-protected, by write control ( wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 7 . figure 7. write mode sequences with wc = 0 (data write enabled) 3 t o p 3 t a r t " y t e 7 r i t e $ e v 3 e l e c t " y t e a d d r e s s $ a t a i n 7 # 3 t a r t 0 a g e 7 r i t e $ e v 3 e l e c t " y t e a d d r e s s $ a t a i n $ a t a i n 7 # $ a t a i n ! ) c 0 a g e 7 r i t e c o n t g d 7 # c o n t g d 3 t o p $ a t a i n . ! # + 2 7 ! # + ! # + ! # + ! # + ! # + ! # + 2 7 ! # + ! # + instructions m24c08-w m24c08-r m24c08-f 16/38 docid023924 rev 4 5.1.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a9/a4, ar e the same. if more bytes are se nt than will fit up to the end of the page, a ?roll-over? occurs, i.e. the by tes exceeding the page end are written on the same page, from location 0. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if write control ( wc ) is low. if write control ( wc ) is high, the contents of the addressed memory location are not modified, an d each data byte is followed by a noack, as shown in figure 8 . after each transferred byte, the internal page address counter is incremented. the transfer is terminated by the bu s master generating a stop condition. figure 8. write mode sequences with wc = 1 (data write inhibited) 3 t o p 3 t a r t " y t e 7 r i t e $ e v s e l e c t " y t e a d d r e s s $ a t a i n 7 # 3 t a r t 0 a g e 7 r i t e $ e v s e l e c t " y t e a d d r e s s $ a t a i n $ a t a i n 7 # $ a t a i n ! ) d 0 a g e 7 r i t e c o n t g d 7 # c o n t g d 3 t o p $ a t a i n . ! # + ! # + . / ! # + 2 7 ! # + ! # + . / ! # + . / ! # + 2 7 . / ! # + . / ! # + docid023924 rev 4 17/38 m24c08-w m24c08-r m24c08-f instructions 37 5.1.3 minimizing write delays by polling on ack the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to ma ke use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 9 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 9. write cycle polling flowchart using ack t?]? ?o ]v ??}p??? $ , h e?? k???]}v ]? ???]vp ?z uu}?? ^??? }v]?]}v ] ?o? ]?z z t a < ???v z ^ e k z ^ e k z ^??? ^?}? ? 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